In many digital communication systems, embedded clock and/or data signals may be recovered from a nonreturn-to-zero (NRZ) encoded high speed serial data stream. Referring now to FIG. 1, a conventional approach to accomplish embedded clock data recovery in an NRZ encoded high speed serial data stream is shown and indicated by the general reference character 100. Differential serial input data stream 120, which may be degraded from the transmitted data by the addition of noise and the attenuation of the signal content, is connected to receiver 119. Receiver 119 amplifies signal 120 to produce serial data stream input 111, which is input to phase detector (with data sampling and decision circuitry) 112 and frequency detector 113. These circuits respectively compare the phase and frequency of signal transitions in the serial data stream (e.g., serial data stream input 111) to the phase and frequency of recovered clock signal 118, the output of variable frequency oscillator (VFO) 117.
Combining or selecting circuitry 115 couples the result of the phase and frequency comparisons to frequency control signal 116 for VFO 117 using one of several methods known in the art. Serial data stream input 111 and recovered clock 118 are also used by the data sampling and decision circuitry portion of block 112 to decide the value of the input data stream at an appropriate transition of recovered clock 118. The output of the data sampling and decision circuitry portion of block 112 is retimed recovered serial data 114, which is now substantially phase coherent with recovered clock 118 and which typically has more robust signal levels than input data stream 120.
Drawbacks of this approach include: (i) relative difficulty in design due to the signal spectrum of the NRZ data, and (ii) susceptibility to false lock, either to a harmonic or 180° out-of-phase (typically when the VFO frequency range is too wide for the frequency of the incoming data 120). Also, as devices get smaller and integration on monolithic devices increases, minimizing power consumption becomes an increasingly important objective. For example, in order to save power when there is no useful data to transmit, transmitters in communications systems may enter a low power mode, in which there are no transitions on the data signaling lines. A further drawback of the approach of FIG. 1 relates to inoperability with transmitter low power modes that do not provide data transitions for clock data recovery (CDR) circuit synchronization.
One common technique to overcome some problems associated with the conventional approach described above with reference to FIG. 1 is to provide a clock data recovery (CDR) circuit with a low speed reference clock having a frequency that has a fraction of the serial data stream frequency. This simplifies the determination of the initial frequency value of the VFO, even when the VFO has a wide frequency range.
Referring now to FIG. 2, a conventional approach using a low speed reference clock is shown and indicated by the general reference character 200. Differential input data stream 220 is coupled to phase detector (with data sampling and decision circuitry) 212 through amplifying receiver 219. Frequency detector 213 compares the frequency of low-speed reference clock 224 (generally a fraction of the serial data stream frequency) with signal 229, the frequency of which is generally recovered clock signal 218 (the VFO 217 output), divided by the frequency division ratio of divider 225. An output of frequency detector 213 is a frequency control signal 226 connected to combining/selecting circuitry 215. Another output of frequency detector 213 is frequency lock signal 221 connected to sequential machine 223, which is initialized by power-on reset signal 228. Outputs from phase detector 212 include frequency control signal 227 to combining/selecting circuitry 215 and control signal(s) 222 to sequential machine 223. These control signals 222 and 227 typically include a lock signal and a “no-signal-transition” signal.
In operation, sequential machine 223 is initialized and sets combining/selecting circuitry 215 to select the output of frequency detector 213. The operation of the loop composed of frequency detector 213, VFO 217, and divider 225 changes the frequency of VFO 217 to be the frequency of reference clock 224 multiplied by the frequency division ratio of divider 225. When frequency lock is achieved, lock indicator control 221 will change the state of sequential machine 223 to cause combining/selecting circuitry 215 to deselect control signal 226 and couple the output of phase detector 212 to frequency control 216 input to VFO 217. At this time, phase detector 212 controls the frequency of VFO 217 largely using data transition phase in the serial data stream. The input data stream should provide (or be monitored to ensure) sufficient data transitions to keep the VFO frequency locked and to compensate for normal frequency variations of VFO 217 and its associated control circuitry. If insufficient data transitions occur over some time interval, or if lock of VFO 217 to data is lost for some other reason (e.g., a temperature or voltage excursion causing a frequency variation greater than the lock range of the phase detector 212), sequential machine 223 changes state and again causes the loop to lock to reference clock 224.
To save power, it is desirable for a transmitter to shut down and transmit no transitions on the data lines when no useful data is available for transmission. This saves power in associated transmitter circuitry by not having to drive data signal transitions merely for purposes of CDR circuit synchronization. However, when no useful data is transmitted, many communications protocols transmit “IDLE” characters containing a sufficient number of transitions to preserve the lock state in a CDR circuit containing a phase detector such as phase detector 212. This sequence is typically referred to as the transmitter entering a “logical idle” state.
When in such a “logical idle” state, it is also desirable to indicate to the receiver if no data is expected to be available for a relatively long period of time, so that the transmitter and/or receiver may enter an even lower power state. Some communications protocols indicate this condition by the transmitter sending a message saying it is about to enter an idle period, subsequently entering the “logical idle” state for a predetermined period of time, and then holding the transmit driver output at a fixed logic level (e.g., a differential voltage indicating a logic state “0”). When useful data is again available for transmission, the transmitter may first prepend to the data a preamble (sometimes called a “training sequence”) that contains sufficient transitions on the data lines to pull the VFO in the receiver into lock. Normal data transmissions can then be resumed.
An alternative signaling scheme to indicate entrance and exit from the idle state is possible when the input data stream is a binary signal being transmitted over a differential pair. A differential signaling scheme sends the data as a voltage and/or current difference between a pair of signal lines where the differential signal lines are in complementary states (e.g., one line may be in the “high” state and the other may be in the “low” state, or vice versa). Essentially, no other states are allowed except those temporary or transitional states that might exist during the transition from one state (e.g., high) to the other (e.g., low). Putting both lines of the pair to a substantially identical voltage or current (e.g., to a voltage midway between the “high” and “low” levels) can indicate a special state. For example, the Peripheral Component Interconnect (PCI) Express protocol defines such a special state of the differential pair coupled to a transmitter as an “electrical idle” state, and it is used to indicate the absence of useful or valid data to transmit. This is a fairly reliable method of signaling such a state because a transmission error on, or a physical defect of, a single line of a differential pair cannot typically cause the false occurrence of this state. However, the approach of FIG. 2 still has a number of shortcomings, in that the phase and/or frequency of recovered clock 218 can drift as long as phase detector 212 controls VFO 217, and CDR circuit 200 must lose its lock before control of the VFO 217 switches over to frequency detector 213. If the phase and/or frequency drift is sufficiently great, the recovered clock and/or data signals may lock onto an out-of-phase signal or a harmonic. On the other hand, reliable recovery of in-phase and frequency-appropriate clock and/or data signals are not necessarily guaranteed if lock is lost.
What is desired is a reliable and simple design approach for CDR circuits more fully operable with low power mode transmitters. Further, it is also desirable to have a relatively quick “wake-up” period to recover clock and/or data signals upon exit from such a low power mode, for example by maintaining at least a frequency lock for the recovered clock signal, or minimizing the phase and/or frequency drift of the recovered clock signal so that it is less likely to lock onto an out-of-phase signal or a harmonic of the incoming differential input signal.